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general description the MAX5500/max5501 integrate four low-power, 12-bit digital-to analog converters (dacs) and four precision output amplifiers in a small, 20-pin package. each nega- tive input of the four precision amplifiers is externally accessible providing flexibility in gain configurations, remote sensing, and high output drive capacity, making the MAX5500/max5501 ideal for industrial-process-con- trol applications. other features include software shut- down, hardware shutdown lockout, an active-low reset which clears all registers and dacs to zero, a user-pro- grammable logic output, and a serial-data output. each dac provides a double-buffered input organized as an input register followed by a dac register. a 16-bit serial word loads data into each input register. the seri- al interface is compatible with spi/qspi/ microwire. the serial interface allows the input and dac registers to be updated independently or simulta- neously with a single software command. the 3-wire interface simultaneously updates the dac registers. all logic inputs are ttl/cmos-logic compatible. the MAX5500 operates from a single +5v power supply, and the max5501 operates from a single +3v power supply. the MAX5500/max5501 are specified over the extended -40? to +105? temperature range. applications industrial process controls automatic test equipment microprocessor ( p)-controlled systems motion control digital offset and gain adjustment remote industrial controls features four 12-bit dacs with configurable output amplifiers +5v or +3v single-supply operation low supply current: 0.85ma normal operation 10 a shutdown mode (MAX5500) force-sense outputs power-on reset clears all registers and dacs to zero capable of recalling last state prior to shutdown spi/qspi/microwire compatible simultaneous or independent control of dacs through 3-wire serial interface user-programmable digital output guaranteed over extended temperature range (-40? to +105?) MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface ________________________________________________________________ maxim integrated products 1 MAX5500 max5501 outa fba fbb fbc fbd dac a dac b dac c dac d refab dac register a decode control input register a dac register b input register b dac register c input register c dac register d input register d 16-bit shift register sr control logic output cs din sclk outb outc outd dout pdl cl v dd agnd dgnd upo refcd functional diagram 19-4368; rev 1; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor, corp. ordering information part pin- package inl (lsb) supply (v) MAX5500 agap+ 20 ssop ?.75 +5 MAX5500bgap+ 20 ssop ? +5 max5501 agap+ 20 ssop ?.75 +3 max5501bgap+ 20 ssop ?2 +3 + denotes a lead(pb)-free/rohs-compliant package. note: all devices are specified over the -40? to +105? operating temperature range. www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (MAX5500 (v dd = +5v ?0%, v refab = v refcd = 2.5v), max5501 (v dd = +3v to +3.6v, v refab = v refcd = 1.25v), v agnd = v dgnd = 0, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values at t a = +25?. output buffer connected in unity-gain configuration (figure 9).) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd............................................................-0.3v to +6v v dd to dgnd ...........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v refab, refcd to agnd ...........................-0.3v to (v dd + 0.3v) out_, fb_ to agnd...................................-0.3v to (v dd + 0.3v) digital inputs to dgnd.............................................-0.3v to +6v dout, upo to dgnd ................................-0.3v to (v dd + 0.3v) continuous current into any pin.......................................?0ma continuous power dissipation (t a = +70?) 20-pin ssop (derate 8.00mw/? above +70?) .........640mw operating temperature range .........................-40? to +105? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static performance (analog section) resolution n 12 bits MAX5500a/max5501a ?.25 ?.75 integral nonlinearity (note 1) inl MAX5500b/max5501b ?.0 lsb differential nonlinearity dnl guaranteed monotonic ?.0 lsb offset error v os ?.5 mv offset-error tempco 6 ppm/ o c MAX5500 -0.3 ?.0 gain error (note 1) ge max5501 -0.7 ?.0 lsb gain-error tempco 1 ppm/ o c MAX5500 100 600 power-supply rejection ratio psrr max5501 100 300 ?/v matching performance (t a = +25 o c) MAX5500 -0.3 ?.0 gain error ge max5501 -0.85 ?.0 lsb offset error v os ?.0 ?.5 mv integral nonlinearity inl (note 1) ?.35 ?.0 lsb reference input reference input range v ref 0v dd - 1.4 v reference input resistance r ref code-dependent, minimum at code 555h 8k ? refer ence c ur r ent i n s hutd ow n 0.01 ?.0 a digital inputs MAX5500a/MAX5500b 2.4 input high voltage v ih max5501a/max5501b 2.0 v input low voltage v il 0.8 v input leakage current i in v in = 0 or v dd ?.1 ?.0 a input capacitance c in 8pf www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (MAX5500 (v dd = +5v ?0%, v refab = v refcd = 2.5v), max5501 (v dd = +3v to +3.6v, v refab = v refcd = 1.25v), v agnd = v dgnd = 0, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values at t a = +25?. output buffer connected in unity-gain configuration (figure 9).) parameter symbol conditions min typ max units digital outputs output high voltage v oh i source = 2ma v dd - 0.5 v output low voltage v ol i sink = 2ma 0.13 0.4 v dynamic performance voltage output slew rate sr 0.6 v/? to ?.5 lsb, v step = 2.5v MAX5500a/MAX5500b 12 output settling time to ?.5 lsb, v step = 1.25v max5501a/max5501b 16 ? output voltage swing rail-to-rail (note 2) 0 to v dd v current into fb_ 0 0.1 ? out_ leakage current in shutdown r l = ?.01 ?.0 a MAX5500a/MAX5500b 15 startup time exiting shutdown mode max5501a/max5501b 20 ? digital feedthrough cs =v dd , f in = 100khz 5 nv ? s digital crosstalk 5nv ? s power supplies MAX5500a/MAX5500b 4.5 5.5 supply voltage v dd max5501a/max5501b 3.0 3.6 v supply current i dd (note 3) 0.85 1.1 ma supply current in shutdown (note 3) 10 20 ? timing characteristics (figure 6) sclk clock period t cp 100 ns sclk pulse-width high t ch 40 ns sclk pulse-width low t cl 40 ns cs fall to sclk rise setup time t css 40 ns sclk rise to cs rise hold time t csh 0ns din setup time t ds 40 ns din hold time t dh 0ns www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (MAX5500 (v dd = +5v ?0%, v refab = v refcd = 2.5v), max5501 (v dd = +3v to +3.6v, v refab = v refcd = 1.25v), v agnd = v dgnd = 0, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values at t a = +25?. output buffer connected in unity-gain configuration (figure 9).) parameter symbol conditions min typ max units MAX5500 80 sclk rise to dout valid propagation delay t d01 c load = 200pf max5501 120 ns MAX5500 80 sclk fall to dout valid propagation delay t d02 c load = 200pf max5501 120 ns sclk rise to cs fall delay t cs0 40 ns cs rise to sclk rise hold time t cs1 40 ns cs pulse-width high t csw 100 ns note 1: guaranteed from code 11 to code 4095 in unity-gain configuration. note 2: accuracy is better than 1.0 lsb for v out = 6mv to (v dd - 60mv), guaranteed by psr test on endpoints. note 3: r l = , digital inputs at dgnd or v dd . integral nonlinearity vs. reference voltage MAX5500 toc01 reference voltage (v) inl (lsb) 3.6 2.8 2.0 1.2 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 0.4 4.4 MAX5500 v dd = 5v r l = 5k ? integral nonlinearity vs. reference voltage MAX5500 toc02 reference voltage (v) inl (lsb) 1.9 1.4 0.9 -0.8 -0.6 -0.4 -0.2 0 -1.0 0.4 2.4 max5501 v dd = 3v r l = 5k ? supply current vs. temperature MAX5500 toc03 temperature ( c) i dd ( a) 110 95 80 65 50 35 20 5 -10 -25 -40 860 870 880 890 900 910 850 -55 125 MAX5500 v dd = 5v code = fff hex typical operating characteristics (t a = +25?, unless otherwise noted.) www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 5 supply current vs. temperature MAX5500 toc04 temperature ( c) i dd ( a) 110 95 80 65 50 35 20 5 -10 -25 -40 740 760 780 800 820 750 770 790 810 830 730 -55 125 max5501 v dd = 3v code = fff hex full-scale error vs. load MAX5500 toc05 load (k ? ) inl (lsb) 10 1 0.1 -4 -3 -2 -1 0 -5 0.01 100 MAX5500 v dd = 5v full-scale error vs. load MAX5500 toc06 load (k ? ) inl (lsb) 10 1 0.1 -4 -3 -2 -1 0 -5 0.01 100 max5501 v dd = 3v supply current vs. supply voltage MAX5500 toc07 v dd (v) i dd ( a) 5.25 5.00 4.75 780 800 820 840 860 880 900 920 940 760 4.50 5.50 MAX5500 v dd = 5v code = fff hex supply current vs. supply voltage MAX5500 toc08 v dd (v) i dd ( a) 3.5 3.4 3.1 3.2 3.3 784 786 788 790 792 794 796 798 782 3.0 3.6 max5501 v dd = 3v code = fff hex analog crosstalk 5v MAX5500 toc09 10 s/div outa 1v/div outb ac-coupled 10mv/div v ref = 2.5v, r l = 5k ? , c l = 100pf daca code switching from 00c hex to fcc hex dacb code set to 800 hex analog crosstalk 3v MAX5500 toc10 10 s/div outa 0.5v/div outb ac-coupled 50mv/div v ref = 1.5v, r l = 5k ? , c l = 100pf daca code switching from 00c hex to fff hex dacb code set to 800 hex dynamic response 5v MAX5500 toc11 10 s/div outa 1v/div v ref = 2.5v, r l = 5k ? , c l = 100pf switching from code 000 hex to fb4 hex output amplifier gain = +2 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 6 _______________________________________________________________________________________ pin description pin name function 1 agnd analog ground 2 fba dac a output amplifier feedback 3 outa dac a output voltage 4 outb dac b output voltage 5 fbb dac b output amplifier feedback 6 refab dac a/dac b reference voltage input 7 cl active-low clear input. cl clears all dacs and registers. cl resets all outputs (out_, upo, and dout) to 0. 8 cs active-low chip-select input 9 din serial data input 10 sclk serial clock input 11 dgnd digital ground 12 dout serial data output 13 upo user-programmable logic output 14 pdl active-low power-down lockout. drive pdl low to lock out software shutdown. 15 refcd dac c/dac d reference voltage input 16 fbc dac c output amplifier feedback 17 outc dac c output voltage 18 outd dac d output voltage 19 fbd dac d output amplifier feedback 20 v dd positive power supply dynamic response 3v MAX5500 toc12 10 s/div outa 0.5v/div v ref = 1.5v, r l = 5k ? , c l = 100pf switching from code 000 hex to fb4 hex output amplifier gain = +1 digital feedthrough 3v (sclk = 100khz) MAX5500 toc13 4 s/div sclk 1v/div outa ac-coupled 10mv/div v ref = 1.5v, r l = 5k ? , c l = 100pf v cs = v pdl = v cl = 3.3v, v din = 0v daca code set to 800 hex digital feedthrough 5v (sclk = 100khz) MAX5500 toc14 2 s/div sclk 2v/div outa ac-coupled 10mv/div v ref = 2.5v, r l = 5k ? , c l = 100pf v cs = v pdl = v cl = 5v, v din = 0v daca code set to 800 hex typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 7 detailed description the MAX5500/max5501 integrate four 12-bit, voltage- output digital-to-analog converters (dacs) that are addressed through a simple 3-wire serial interface. the devices include a 16-bit data-in/data-out shift register. each internal dac provides a doubled-buffered input composed of an input register and a dac register (see the functional diagram ). the negative input of each amplifier is externally accessible. the dacs are inverted rail-to-rail ladder networks that convert 12-bit digital inputs into equivalent analog out- put voltages in proportion to the applied reference volt- age inputs. dacs a and b share the refab input, while dacs c and d share the refcd input. the two reference inputs allow different full-scale output voltage ranges for each pair of dacs. figure 1 shows a simpli- fied circuit diagram of one of the four dacs. reference inputs the two reference inputs accept positive dc and ac signals. the voltage at each reference input sets the full-scale output voltage for the two corresponding dacs. the reference input voltage range is 0v to (v dd - 1.4v). the output voltages (v out_ ) are represented by a digitally programmable voltage source as: v out_ = (v ref x nb/4096) x gain where nb is the numeric value of the binary input code (0 to 4095) of the dac. v ref is the reference voltage. gain is the externally set voltage gain. the impedance at each reference input is code-depen- dent, ranging from a low value of 10k ? when both dacs connected to the reference accept an input code of 555 hex, to a high value exceeding giga-ohms with an input code of 000 hex. the load regulation of the ref- erence source affects the performance of the devices as the input impedance at the reference inputs is code dependent. the refab and refcd reference inputs provide a 10k ? guaranteed minimum input impedance. when the same voltage source drives the two reference inputs, the effective minimum impedance is 5k ? . a volt- age reference with an excellent load regulation of 0.0002mv/ma, such as the max6033, is capable of dri- ving both reference inputs simultaneously at 2.5v. driving refab and refcd separately improves refer- ence accuracy. the refab and refcd inputs enter a high-impedance state, with a typical input leakage current of 0.02?, when the MAX5500/max5501 are in shutdown. the ref- erence input capacitance is also code dependent and typically ranges from 20pf with an input code of all 0s to 100pf with an input code of all 1s. output amplifiers all dac outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6v/?. access to the inverting input of each output amplifier provides the greater flexibility in output gain setting/signal condition- ing (see the applications information section). with a full-scale transition at the output, the typical set- tling time to within ?.5 lsb is 12? when the output is loaded with 5k ? in parallel with 100pf. a load of less than 2k ? at the output degrades performance. see the typical operating characteristics for the output dynamic responses and settling performances of the amplifiers. power-down mode the MAX5500/max5501 feature a software-program- mable shutdown that reduces supply current to a typi- cal value of 10?. drive pdl high to enable the shutdown mode. write 1100xxxxxxxxxxxx as the input-control word to put the device in power-down mode (table 1). in power-down mode, the output amplifiers and the ref- erence inputs enter a high-impedance state. the serial interface remains active. data in the input registers is retained in power-down, allowing the devices to recall the output states prior to entering shut- down. start up from power-down either by recalling the previous configuration or by updating the dacs with new data. allow 15? for the outputs to stabilize when powering up the devices or bringing the devices out of shutdown. out_ fb_ shown for all 1s on dac d0 d9 d10 d11 2r 2r 2r 2r 2r rrr ref_ agnd figure 1. simplified dac circuit diagram www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 8 _______________________________________________________________________________________ sclk din dout* cs sk so si* i/o MAX5500 max5501 microwire port *the dout-si connection is not required for writing to the MAX5500/max5501, but can be used for readback purposes. figure 2. connections for microwire serial-interface configurations the MAX5500/max5501s?3-wire serial interface is compatible with both microwire (figure 2) and spi/qspi (figure 3). the serial input word consists of two address bits and two control bits followed by 12 data bits (msb first), as shown in figure 4. the 4-bit address/control code determines the MAX5500/ max5501s?response outlined in table 1. the connec- tion between dout and the serial-interface port is not necessary, but may be used for data echo. data held in the shift register can be shifted out of dout and returned to the ? for data verification. the digital inputs of the MAX5500/max5501 are double buffered. depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the dac register(s), the dac register(s) can be loaded directly, or all four dac registers can be updated simultaneously from the input registers (table 1). serial-interface description the MAX5500/max5501 require 16 bits of serial data. table 1 lists the serial-interface programming com- mands. for certain commands, the 12 data bits are don?-care bits. data is sent msb first and can be sent in two 8-bit packets or one 16-bit word ( cs must remain low until 16 bits are transferred). the serial data is com- posed of two dac address bits (a1, a0) and two control bits (c1, c0), followed by the 12 data bits d11?0 (figure 4). the 4-bit address/control code determines: ? the register(s) to be updated ? the clock edge on which data is to be clocked out through the serial-data output (dout) ? the state of the user-programmable logic output (upo) ? if the device is to enter shutdown mode (assuming pdl is high) ? how the device is configured when exiting out of shutdown mode dout* din sclk cs miso* mosi sck i/o spi/qspi port ss +5v cpol = 0, cpha = 0 *the dout-miso connection is not required for writing to the MAX5500/max5501, but can be used for readback purposes. MAX5500 max5501 figure 3. connections for spi/qspi msb............................................................................................................................ .....lsb msb...........................................................................................lsb 16 bits of serial data address bits control bits data bits 4 address/ control bits d11..............................................................................................d0 a1 a0 c1 c0 12 data bits figure 4. serial-data format www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 16-bit serial word a1 a0 c1 c0 d11................d0 msb lsb function 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 12-bit dac data 12-bit dac data 12-bit dac data 12-bit dac data load input register a; dac registers unchanged. load input register b; dac registers unchanged. load input register c; dac registers unchanged. load input register d; dac registers unchanged. 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 12-bit dac data 12-bit dac data 12-bit dac data 12-bit dac data load input register a; all dac registers updated. load input register b; all dac registers updated. load input register c; all dac registers updated. load input register d; all dac registers updated. 0 1 0 0 xxxxxxxxxxxx update all dac registers from their respective input registers (startup). 1 0 0 0 12-bit dac data load all dac registers from shift register (startup). 1 1 0 0 xxxxxxxxxxxx shutdown (provided pdl = 1) 0 0 1 0 xxxxxxxxxxxx upo goes low (default) 0 1 1 0 xxxxxxxxxxxx upo goes high 0 0 0 0 xxxxxxxxxxxx no operation (nop) to dac registers 1 1 1 0 xxxxxxxxxxxx mode 1, dout clocked out on sclk? rising edge. all dac registers updated. 1 0 1 0 xxxxxxxxxxxx mode 0, dout clocked out on sclk? falling edge. all dac registers updated (default). table 1. serial-interface programming commands figure 5 shows the serial-interface timing requirements. the cs input must be low to enable the dac? serial interface. when cs is high, the interface control circuitry is disabled. cs must go low for at least t css before the rising serial clock (sclk) edge to properly clock in the first bit. when cs is low, data is clocked into the internal shift register through the serial data input (din) on the rising edge of sclk. the maximum guaranteed clock frequency is 10mhz. data is latched into the appropriate input/dac registers on the rising edge of cs . the programming command ?oad-all-dacs-from-shift- register?allows all input and dac registers to be simul- taneously loaded with the same digital code from the input shift register. the no operation (nop) command leaves the register contents unaffected. this feature is used in a daisy-chain configuration (see the daisy chaining devices section). the command to change the clock edge on which seri- al data is shifted out of dout also loads data from all input registers to their respective dac registers. serial-data output (dout) the serial-data output, dout, is the internal shift regis- ter? output. the MAX5500/max5501 can be pro- grammed so that data is clocked out of dout on the rising edge of sclk (mode 1) or the falling edge (mode 0). in mode 0, output data at dout lags input data at din by 16.5 clock cycles, maintaining compatibility with microwire, spi/qspi, and other serial interfaces. in mode 1, output data lags input data by 16 clock cycles. on power-up, dout defaults to mode 0 timing. user-programmable logic output (upo) the user-programmable logic output, upo, allows an external device to be controlled through the MAX5500/max5501 serial interface (table 1). low-power, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 9 www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 10 ______________________________________________________________________________________ cs sclk din dout (mode 1) msb from previous write msb from previous write command executed 9 8 16 1 a0 a1 d0 c1 c0 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 dout (mode 0) a0 a1 d0 a1 c1 c0 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 a0 a1 d0 a1 c1 c0 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 data packet (n) data packet (n-1) data packet (n) data packet (n-1) data packet (n) figure 5. serial-interface timing diagram sclk din dout t cso t css t cl t ch t cp t do1 t csw t cs1 t do2 t csh t ds t dh cs figure 6. detailed serial-interface timing diagram power - down lockout ( pdl ) drive power-down lockout, pdl , low to disable software shutdown. when in shutdown, transitioning pdl from high to low wakes up the device with the output set to the state prior to shutdown. use pdl to asynchronously wake up the device. daisy chaining devices the MAX5500/max5501 can be daisy chained by con- necting dout of one device to din of another device (figure 7). each dout output of the MAX5500/max5501 includes an internal active pullup. the sink/source capability of dout determines the time required to discharge/charge a capacitive load. see the serial-data-out v oh and v ol specifications in the electrical characteristics. figure 8 shows an alternate method of connecting sev- eral MAX5500/max5501 devices. in this configuration, the data bus is common to all devices. data is not shift- ed through a daisy chain. more i/o lines are required in this configuration because a dedicated chip-select input ( cs ) is required for each ic. www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 11 din cs to other serial devices MAX5500 max5501 sclk din cs dout MAX5500 max5501 sclk din cs dout MAX5500 max5501 sclk din cs dout sclk figure 7. daisy chaining MAX5500/max5501 to other serial devices MAX5500 max5501 din sclk cs MAX5500 max5501 din sclk cs MAX5500 max5501 din sclk cs din sclk cs1 cs2 cs3 figure 8. multiple MAX5500/max5501 devices sharing a common din line www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 12 ______________________________________________________________________________________ dac contents analog output msb lsb 4095 1111 1111 1111 +v ref ( ? ) 4096 2049 1000 0000 0001 +v ref ( ? ) 4096 2048 +v ref 1000 0000 0000 +v ref ( ? ) = 4096 2 2047 0111 1111 1111 +v ref ( ? ) 4096 1 0000 0000 0001 +v ref ( ? ) 4096 0000 0000 0000 0v table 2. unipolar code table dac contents analog output msb lsb 2047 1111 1111 1111 +v ref ( ? ) 2048 1 1000 0000 0001 +v ref ( ? ) 2048 1000 0000 0000 0v 1 0111 1111 1111 -v ref ( ? ) 2048 2047 0000 0000 0001 -v ref ( ? ) 2048 2048 0000 0000 0000 -v ref ( ? ) = -v ref 2048 table 3. bipolar code table note: 1 lsb = (v ref ) ( 4096 ) 1 MAX5500 max5501 dac a dac b dac c dac d outa fba fbb fbc fbd outb outc outd dgnd agnd refab refcd reference inputs +5v v dd figure 9. unipolar output circuit MAX5500 max5501 dac a dac b dac c dac d v refab = v refcd = 2.5v outa 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? outb outc outd dgnd agnd refab refcd reference inputs +5v v dd fba fbb fbc fbd figure 10. unipolar rail-to-rail output circuit applications information unipolar output for a unipolar output, the output voltages and the refer- ence inputs are of the same polarity. figure 9 shows the MAX5500/max5501 unipolar output circuit, which is also the typical operating circuit. table 2 lists the unipo- lar output codes. see figure 10 for rail-to-rail outputs. figure 10 shows the MAX5500/max5501 with the output amplifiers con- figured with a closed-loop gain of +2 to provide 0 to 5v full-scale range with a 2.5v external reference voltage. bipolar output figure 11 shows the MAX5500/max5501 configured for bipolar operation. v out = v ref [(2nb/4096) - 1] where nb is the numeric value of the dac? binary input code. table 3 shows digital codes (offset binary) and corresponding output voltages for the circuit of figure 11. www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 13 digitally programmable current source the circuit of figure 12 places an npn transistor (2n3904 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional cur- rent source. this circuit drives 4ma to 20ma current loops, which are commonly used in industrial-control applications. the output current is calculated with the following equation: i out = (v ref /r) x (nb/4096) where nb is the numeric value of the dac? binary input code and r is the sense resistor shown in figure 12. power-supply considerations on power-up, all input and dac registers are cleared (set to zero code) and d out is in mode 0 (serial data is shifted out of dout on the clock? falling edge). for rated MAX5500/max5501 performance, limit v refab / v refcd to 1.4v below v dd . bypass v dd with a 4.7? capacitor in parallel with a 0.1? capacitor to agnd. use short lead lengths and place the bypass capaci- tors as close as possible to the supply inputs. grounding and layout considerations digital or ac transient signals between agnd and dgnd create noise at the analog outputs. connect agnd and dgnd together at the dac, and then con- nect this point to the highest-quality ground available. good pcb ground layout minimizes crosstalk between dac outputs, reference inputs, and digital inputs. reduce crosstalk by keeping analog lines away from digital lines. do not use wire-wrapped boards. chip information process: bicmos dac v out +5v -5v r1 = r2 = 10k ? 0.1% MAX5500 max5501 ref_ r1 r2 fb_ out_ figure 11. bipolar output circuit dac_ MAX5500 max5501 ref_ out_ r i out 2n3904 v l fb_ figure 12. digitally progammable current source www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface 14 ______________________________________________________________________________________ package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 20 ssop a20-2 21-0056 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v dd fbd outd outc outb outa fba agnd top view fbc refcd pdl upo cs cl refab fbb 12 11 9 10 dout dgnd sclk din ssop MAX5500 max5501 + pin configuration www.datasheet.co.kr datasheet pdf - http://www..net/
MAX5500/max5501 low-power, quad, 12-bit voltage-output dacs with serial interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 11/08 initial release 1 4/09 removed future product asterisk from max5501 in ordering information table and updated electrical characteristics table 1? www.datasheet.co.kr datasheet pdf - http://www..net/

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